DESAIN PERALATAN FUNGSI BINER 3 BIT UNTUK OPERASI PENJUMLAHAN DAN PENGURANGAN DENGAN MEMANFAATKAN PROGRAM VHDL
A, M. THANIF (2004) DESAIN PERALATAN FUNGSI BINER 3 BIT UNTUK OPERASI PENJUMLAHAN DAN PENGURANGAN DENGAN MEMANFAATKAN PROGRAM VHDL. Undergraduate thesis, Universitas Muhammadiyah Jember.
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| Dosen Pembimbing: | RUSGIANTO, RUSGIANTO and SUPENO, BAMBANG | NIDN#, NIDN# |
|---|---|
| Item Type: | Thesis (Undergraduate) |
| Subjects: | 600 Technology and Applied Science > 620 Engineering |
| Divisions: | Faculty of Engineering > Department of Electrical Engineering (S1) |
| Depositing User: | Hendri UF | hendri@unmuhjember.ac.id |
| Date Deposited: | 12 Jan 2023 07:53 |
| Last Modified: | 12 Jan 2023 07:53 |
| URI: | https://repository.unmuhjember.ac.id/id/eprint/15936 |
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