A, M. THANIF (2004) DESAIN PERALATAN FUNGSI BINER 3 BIT UNTUK OPERASI PENJUMLAHAN DAN PENGURANGAN DENGAN MEMANFAATKAN PROGRAM VHDL. Undergraduate thesis, Universitas Muhammadiyah Jember.
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M. THANIF A.-01162041.pdf Restricted to Repository staff only Download (29MB) |
| Item Type: | Thesis (Undergraduate) | |||||||||
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| Subjects: | 600 Technology and Applied Science > 620 Engineering | |||||||||
| Divisions: | Faculty of Engineering > Department of Electrical Engineering (S1) | |||||||||
| Department: | S1 Teknik Elektro | |||||||||
| Depositing User: | Hendri UF | |||||||||
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| Date Deposited: | 12 Jan 2023 07:53 | |||||||||
| Last Modified: | 12 Jan 2023 07:53 | |||||||||
| URI: | http://repository.unmuhjember.ac.id/id/eprint/15936 |
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